Profile

Assistant Professor in the field of Electronics & Communication Engineering

Nanoelectronics, Semiconductor Device Modelling, Tunnel FETs, NCFETs, Emerging Semiconductor Devices, Device Circuit Co-design

  • PhD

    Indian Institute of Technology Roorkee
    Department of Electronics and Communication Engineering (Microelectronics and VLSI)

  • Master of Engineering (M.E.)

    Jadavpur University
    Department of Electronics and Telecommunication Engineering

  • Bachelor of Engineering (B.E.)

    Government Engineering College Bilaspur
    Department of Electronics and Telecommunication Engineering

  • November 2019-March 2020 Post Doctoral Fellow

    Karlsruhe Institute of Technology Germany

  • September 2019-November 2019 Research Associate

    Indian Institute of Technology Roorkee

My courses

Current & Previous

Course Code Course name Category Institute Department Link
OE9_c Advanced Semiconductor Devices UG/PhD PDPM-IIITDMJ Electronics & Communication Engineering
ECOE_c VLSI Device Modelling PG/ PDPM-IIITDMJ Electronics & Communication Engineering
Course Code Course name Category Institute

Research

Areas or Specialisation / Project Activities / Publications / Books

Microelectronics and VLSI

  • List of Journal Papers:

    1. Navjeet Bagga, Nitanshu Chauhan, Shashank Banchhor, Divyam Gupta and S. Dasgupta, “Demonstration of a Novel Tunnel FET with Channel Sandwiched by Drain,” Semi. Sci. and Tech. IOP, vol. 35, Nov. 2019.
    2. Navjeet Bagga, Nitanshu Chauhan, Divyam Gupta and S. Dasgupta, “A Novel Twofold Tunnel FET with Reduced Miller Capacitance: Proposal and Investigation,” IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3202-3208, Jul. 2019.
    3. Navjeet Bagga, Anil Kumar and S. Dasgupta, “Demonstration of a Novel Two Source Region Tunnel FET,” IEEE Transactions on Electron Devices, vol. 64, issue 12, pp. 5256-5262, Oct. 2017.
    4. Navjeet Bagga and S. Dasgupta, “Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET, IEEE Trans. Electron Devices , vol. 64, issue 2, pp. 606 – 613, 2017.
    5. Navjeet Bagga, Anil Kumar, A. Bhattacharjee and S. Dasgupta, “Performance evaluation of a novel GAA Schottky Junction TFET with heavily doped pocket, Superlattices and Microstructures, 2017.
    6. Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, “A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges,” Journal of Computational Electronics, doi: 10.1007/s10825-017-1030-7, pp. 1-10, 2017.
    7. Navjeet Bagga, Saheli Sarkhel and S. K. Sarkar, “Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance,” IETE Journal of Research, vol. 62, no. 6, pp. 786-794, 2016.
    8. Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, “Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor,” Journal of Computational Electronics, vol. 15, no. 1, pp. 104–114, 2016.
    9. Navjeet Bagga and S. K. Sarkar, “An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET, IEEE Trans. Electron Devices , vol. 62, no. 7, pp. 2136 – 2142, 2015.

    List of Conference Papers:

    1. Nitanshu Chauhan, Govind Bajpai, Shashank Banchhor, and Navjeet Bagga, "Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification," 24th International Symposium on VLSI Design and Test (VDAT), Jul. 2020.
    2. Navjeet Bagga, Nitanshu Chauhan, A. Bulusu and S. Dasgupta, “Demonstration of Novel Ferroelectric-Dielectric Tunnel FET, IEEE Proc. of MOS-AK, 2019.
    3. Navjeet Bagga and S. Dasgupta, “Demonstration of Novel Structures for Improvement in Performance of Tunnel FETs,” Ph.D. Forum at VLSI Design Conference, 2019.
    4. Nitanshu Chauhan, Navjeet Bagga, Shashank Banchhor, S. Dasgupta and A. Bulusu, “Simulation Study of Transient Negative Capacitance with Stabilization and Amplification,” Proc. IWPSD, 2019.
    5. Divyam Gupta, Navjeet Bagga and S. Dasgupta, “Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study,” Proc. IEEE ICEDSS, 2018.
    6. Navjeet Bagga and S. Dasgupta, “Analytical Threshold Voltage Model of Gate All Around Triple Metal Tunnel FET,” Proc. IEEE of ICEDSS, pp. 146-149, Mar. 2017.
    7. Navjeet Bagga, Anil Kumar and S. Dasgupta, “SOI Based Double Source Tunnel FET (DS-TFET) with High On-Current and Reduced Turn-on Voltage,” Proc. IEEE of MIEL, Serbia, Europe, 2017.
    8. Navjeet Bagga, Saheli Sarkhel and S. K. Sarkar, “Analytical Model for ID-VD characteristics of a Triple Metal Double Gate TFET,” Proc. IEEE ICCCA, 2016.
    9. Navjeet Bagga, Saheli Sarkhel and S. K. Sarkar, “Recent Research Trends in Gate Engineered Tunnel FET for Improved Current Behavior by subduing the Ambipolar Effects: A Review,” Proc. IEEE ICCCA, 2015.
    10. P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “A comparative analysis of Nano SON DMDG MOSFET using Hafnium oxide as dielectric for better performance,” Proc. IEEE ICCCS, 2015.
    11. P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “Analysis and Simulation of Dual Metal Double Gate SON MOSFET using Hafnium Dioxide for Better Performance,” Proc. of IET, 2015.
    12. Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, " Analytical Modeling and Simulation of Work function Engineered Gate Junction-less high-k dielectric Double Gate MOSFET: A Comparative Study," Proc. of IET, 2015.

M. Tech.

Roll no Name Status Year Specialization Co-guide

Ph. D.

Roll no Name Status Year Specialization Co-guide

Contact me

Feel free to contact

    Navjeet Bagga

     navjeet@iiitdmj.ac.in

     

     

     

     

     

     

     (Fax) 91-

     Download CV

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