Assistant Professor in the field of Electronics & Communications Engineering
- Ph.D. in Electronics and Telecommunication Engineering
Institute of Engineering and Technology, D.A.V.V. Indore
- M.Tech in Embedded Systems
School of Electronics, D.A.V.V. Indore
- B.E. in Electronics and Communication Engineering
- Since March 2020- Assistant Professor, Electronics and Communication Department
PDPM IIITDM Jabalpur
- July 2013-February 2020 Lecturer, Electronics & Telecommunication department
Institute of Engineering and technology, Devi Ahilya University, Indore
Current & Previous
|Course Code||Course name||Category||Institute|
|OE3||Digital System Design||PG/PhD||IIITDM Jabalpur|
|OE2||Low Power VLSI Design||PG/PhD||IIITDM Jabalpur|
|MT502||Concepts of Electronic Devices||PG/||IIITDM Jabalpur|
Areas or Specialisation / Project Activities / Publications / Books
Low Power Memory Design, VLSI Circuit and System Design, Power Reduction Techniques
- Prashant Kumar, Meena Panchore, Pushpa Raikwal, Kanchan Cecil "Performance Investigation of Ge DLTFET Based Digital Integrated Circuit" International Journal of Electronics Letters, June 2022. (Impact factor: 0.933)
- Pushpa Raikwal, Ambika Prasad Shah and Vaibhav Neema “A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications” Journal of Circuits, Systems, and Computers, Vol. 30, No. 13, ISSN (online): 1793-6454,pp.1-21, 4 May 2021. (SCI with 1.56 impact factor)
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability” Journal of VLSI Design Tools and Technology, Volume 7, Issue 3, ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print), pp. 1-10, 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “A New 8T SRAM Circuit with Low and High Data Stability Idle Mode at 70nm Technology” Oriental Journal of Computer Science& Technology, Vol. 10, No.1, and ISSN: 0974-6471, pp. 86-93, March 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Implementation of Low Power High Speed 64-Bit Memory Unit Using 8t Sram Cell At 70 Nm Technology” imanager’s Journal on Electronics Engineering, Vol. 8, ISSN: 2249-0760 pp. 26-33, June - August 2018.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Comparative Analysis of Various Existing NT SRAM cells with High Speed Low Power 8T SRAM Cell”, Journal of VLSI Design Tools and Technology, Volume 7, Issue 2, ISSN: 2249-474X (Online), ISSN: 2321- 6492 (Print), pp. 30-36, 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma "Cluster Based Sleep TransistorApproach for Low Power 6T SRAM Cell" Journal of VLSI Design Tools and Technology,ISSN: 2249- 474X (online), ISSN: 2321-6492(print) Volume 6, Issue 1, pp. 41-48, 2016.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Performance Analysis of Various Techniques on 6T SRAM Cell”, i-manager’s Journal on Circuits and Systems, Volume 3, Issue 2, ISSN: 2322 – 035X (Online), ISSN: 02321-7502 (Print), pp. 29-34, Mar-May 2015.
- Pushpa Raikwal, V. Neema, and S. Katiyal, ‘Low Power with Improved Noise Margin for Domino CMOS NAND Gate’, International Journal of Computational Engineering Research (IJCER), Mar-Apr 2012, Vol. 2, Issue No.2, pp. 520-525.
- Pushpa Raikwal, V. Neema, and S. Katiyal, ‘Low Power High Speed with Improved Noise Margin for Domino CMOS Inverter’, Indian Journal of Applied Research (IJAR) April 2012,Vol. 1, Issue No.7, pp. 86-88.
- International Conferences
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “High Speed 8T SRAM Cell Design with Improved Read Stability at 180nm Technology” International Conference on Electronics, Communication and Aerospace Technology (ICECA 2017) pp. 563-568, 20-22 April 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Design and Analysis of Low Power Single Ended 8T (4X4) SRAM Cell at 180nm Technology” International Conference on Signal Processing, Communication, Power and Embedded System, Paralakhemundi, Odissa, India, pp. 312-316, 3-5 October 2016.
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