Profile
Assistant Professor in the field of Electronics & Communications Engineering
Low Power Memory Design, VLSI Circuit and System Design, Device and Circuit Co-design approach, FPGA Implementation
- Ph.D. in Electronics and Telecommunication Engineering
Institute of Engineering and Technology, D.A.V.V. Indore
December 2018 - M.Tech in Embedded Systems
School of Electronics, D.A.V.V. Indore
- B.E. in Electronics and Communication Engineering
I.G.E.C. Sagar
- Since March 2020- Assistant Professor, Electronics and Communication Department
PDPM IIITDM Jabalpur
- July 2013-February 2020 Lecturer, Electronics & Telecommunication department
Institute of Engineering and technology, Devi Ahilya University, Indore
My courses
Current & Previous
| Course Code | Course name | Category | Institute |
|---|---|---|---|
| OE3 | Digital System Design | PG/PhD | IIITDM Jabalpur |
| OE2 | Low Power VLSI Design | PG/PhD | IIITDM Jabalpur |
| MT502 | Concepts of Electronic Devices | PG/ | IIITDM Jabalpur |
Research
Areas or Specialisation / Project Activities / Publications / Books
Memory Design, VLSI System Design
- Device-Circuit Co-Design Approach for Junction-less FET (JLFET) /Doping-less JLFET (DL-JLFET) Digital Circuits and Memory applications.
Faculty Initiation Grant, PDPM IIITDM Jabalpur: 7.10 Lakh (Ongoing)
- Lifetime Reliability Analysis and Mitigation Techniques for High Performance Digital Integrated Circuits
Sponsored by Madhya Pradesh Council of Science & Technology (MPCST), Bhopal: 7:90 Lakh (Ongoing)
- Patent
- 1. Pushpa Raikwal, “An 8T SRAM Circuit with Low Leakage and High Data Stability at Idle Mode” International Patent, Status:Granted, File Number: 202023107182.
- Publications in Journals/Conferences
- Pushpendra Dwivedi, Meena Panchore, Pushpa Raikwal, “Design of Radiation Hardened SRAM Cell using Dopingless Transistor for Space Applications,” Journal of Electrical Engineering & Technology, Springer, March 2024. (Impact Factor 1.9) https://doi.org/10.1007/s42835-024-01851-6
- Nisha Dewangan, Chithraja Rajan, Meena Panchore, Pushpa Raikwal, “A Highly Sensitive MOSFET Gas Sensor based on Charge Plasma and Catalytic Metal Gate,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol.36, Issue 6, pp.1-9, November 2023. (Impact factor: 1.60). DOI:10.1002/jnm.3191
- Pushpa Raikwal, Prashant Kumar, Meena Panchore, Pushpendra Dwivedi and Kanchan Cecil, “Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design” Electronics, Vol.12, ISSN: 2079-9292, pp. 1-10,24 July 2023. (Impact factor: 2.9).
- Prashant Kumar, Meena Panchore, Pushpa Raikwal, Kanchan Cecil "Performance Investigation of Ge DLTFET Based Digital Integrated Circuit" International Journal of Electronics Letters, June 2022. (Impact factor: 0.933)
- Pushpa Raikwal, Ambika Prasad Shah and Vaibhav Neema “A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications” Journal of Circuits, Systems, and Computers, Vol. 30, No. 13, ISSN (online): 1793-6454, pp.1-21, 4 May 2021. (Impact factor: 1.56)
- Swati Verma, Pushpa Raikwal, Meena Panchore, “Impact of Gamma Rays on Emerging Devices for Photonic Applications,” International Conference on Machine vision and Augmented Intelligence, NIT Patna, Bihar, India, 24-25th November 2023.
- Pushpendra Dwivedi, Meena Panchore, Pushpa Raikwal, Akash Agarwal, “Comparison of Different CIC filter architectures on the basis of a novel parameter called Noise Factor for Sigma-Delta based ADCs.” International Conference on Machine vision and Augmented Intelligence, NIT Patna, Bihar, India, 24-25th November 2023.
- Kanchan Cecil, Ashish Jha, Meena Panchore, Pushpa Raikwal, “Dopingless JLFET Based 8TSRAM Cell Design for Enhanced Performance and Stability” International Conference on Machine vision and Augmented Intelligence, NIT Patna, Bihar, India, 24-25th November 2023.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “High Speed 8T SRAM Cell Design with Improved Read Stability at 180nm Technology” International Conference on Electronics, Communication and Aerospace Technology (ICECA 2017) pp. 563-568, 20-22 April 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Design and Analysis of Low Power Single Ended 8T (4X4) SRAM Cell at 180nm Technology” International Conference on Signal Processing, Communication, Power and Embedded System, Paralakhemundi, Odissa, India, pp. 312-316, 3-5 October 2016.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability” Journal of VLSI Design Tools and Technology, Volume 7, Issue 3, ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print), pp. 1-10, 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “A New 8T SRAM Circuit with Low and High Data Stability Idle Mode at 70nm Technology” Oriental Journal of Computer Science& Technology, Vol. 10, No.1, and ISSN: 0974-6471, pp. 86-93, March 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Implementation of Low Power High Speed 64-Bit Memory Unit Using 8t Sram Cell At 70 Nm Technology” imanager’s Journal on Electronics Engineering, Vol. 8, ISSN: 2249-0760 pp. 26-33, June - August 2018.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Comparative Analysis of Various Existing NT SRAM cells with High Speed Low Power 8T SRAM Cell”, Journal of VLSI Design Tools and Technology, Volume 7, Issue 2, ISSN: 2249-474X (Online), ISSN: 2321- 6492 (Print), pp. 30-36, 2017.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma "Cluster Based Sleep TransistorApproach for Low Power 6T SRAM Cell" Journal of VLSI Design Tools and Technology,ISSN: 2249- 474X (online), ISSN: 2321-6492(print) Volume 6, Issue 1, pp. 41-48, 2016.
- Pushpa Raikwal, Vaibhav Neema and Ajay Verma “Performance Analysis of Various Techniques on 6T SRAM Cell”, i-manager’s Journal on Circuits and Systems, Volume 3, Issue 2, ISSN: 2322 – 035X (Online), ISSN: 02321-7502 (Print), pp. 29-34, Mar-May 2015.
- Pushpa Raikwal, V. Neema, and S. Katiyal, ‘Low Power with Improved Noise Margin for Domino CMOS NAND Gate’, International Journal of Computational Engineering Research (IJCER), Mar-Apr 2012, Vol. 2, Issue No.2, pp. 520-525.
- Pushpa Raikwal, V. Neema, and S. Katiyal, ‘Low Power High Speed with Improved Noise Margin for Domino CMOS Inverter’, Indian Journal of Applied Research (IJAR) April 2012,Vol. 1, Issue No.7, pp. 86-88.
M. Tech./M.Des.
| Roll no | Name | Status | Year | Specialization | Co-guide |
|---|---|---|---|---|---|
| 20MECM06 | Priyanka Gupta | Completed | 2022 | Cost effective realization of RRAM array | Dr. Koushik Dutta |
| 22mecv03 | Sambit Jena | Ongoing | 2023 | Implementation of Reliable Memory using VHDL | |
| 21MECV05 | Vatsal Sompura | Completed | 2023 | NVM Memory Design |
Ph. D.
| Roll no | Name | Status | Year | Specialization | Co-guide |
|---|---|---|---|---|---|
| 21PECE07 | Swati Verma | Ongoing | 2022 | Investigation of Nano Materials for Device and Circuit Applications | Dr. Neeraj Kumar Jaiswal |
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